This application claims the priority benefit of Taiwan application serial no. 90101425, filed Jan. 20, 2001.
1. Field of Invention
The present invention relates generally to a cavity down ball grid array package (CDBGA) and a fabrication method thereof. More particularly, the present invention relates to an improved CDBGA package with high reliability.
2. Description of Related Art
With the increasing need for high-density devices for use in lightweight, portable electronics, there has been a gradual shift in the sizes of integrated circuits and their package configurations. This gradual shift has resulted in developing various techniques for different package types.
A ball grid array (BGA) package is a common packaging method in the field of electronic packages. The BGA package utilizes tape or other adhesive materials to adhere a back surface of a chip onto a die pad of a substrate. A plurality of bonding pads are electrically connected to a plurality of nodes of the substrate by conductive wires. A molding compound encapsulates the chip, conductive wires and nodes. A plurality of solder balls are formed on the nodes of the substrate. The above-mentioned structure of a BGA package can utilize solder balls to electrically connect to external circuits. The layout of the solder balls of the BGA package is in a matrix form and it is suitable for a high-density package because it can contain a large quantity of external circuits.
However, although the packaging size is reduced, the integration of the device is increased. Thus the heat produced per unit of area of the device increases. Therefore a heat dissipation problem occurs. For a BGA package, a cavity down ball grid array (CDBAG) package has better heat dissipation because the back surface of the chip is in contact with a heat spreader, and heat is transferred through the heat spreader to the external environment. Thus, the structure of the CDBGA package is often utilized.
FIGS. 1-4 are schematic cross-sectional views of fabricating a CDBGA package in accordance with U.S. Pat. No. 6,020,617.
Referring to FIG. 1 and FIG. 1A, wherein the FIG. 1A depicts a top view of FIG. 1, shows a thermal dissipating substrate 110 comprising a heat spreader 130 and a ground plate 140. The ground plate 140 is adhered onto a surface 132 of the heat spreader 130 by an adhesive material 120. An opening 142 is formed in the ground plate 140. Thus, a cavity is formed in the center of the thermal dissipating substrate 110.
A loop-shaped first node 146 and a plurality of second nodes 148 are selective plated on a surface 144 of the ground plate 140. The first node and the second nodes are made of materials selected from a group consisting of gold and silver. A black oxide treatment is carried out to roughen a surface 144 of the ground plate 140, so that the adhesion between the ground plate and the substrate (not shown) can be increased.
Referring to FIG. 2, a substrate 150 comprising an insulating layer 160 and a patterned trace layer 170. The insulating layer 160 of the substrate 150 is adhered onto the surface 144 of the ground plate 140 by an adhesive material 122. A plurality of ground pads 172, ball pads 174 and nodes 176 are formed on the patterned trace layer 170. The substrate 150 further comprises a solder mask layer 180 that protects the patterned trace layer 170 and exposes the ground pads 172, the ball pads 174 and nodes 176. A plurality of vias 190, which are formed on the substrate 150, are pierced through the patterned trace layer 170, insulating layer 160 and adhesive material 122, and the second nodes 148 are exposed.
A stencil printing method is utilized to fill a conductive material into the vias 190 in order to electrically connect the ground pads 172 to the second nodes 148.
Referring to FIG. 3, a chip 200 has an active surface 202 and a corresponding back surface 204, wherein a plurality of bonding pads 206 and ground pads 208 are formed on the active surface 202. The back surface 204 of the chip 200 is adhered onto a surface 132 of the heat spreader 130 by an adhesive material 124. The bonding pads 206 are electrically connected to the node 176 by a plurality of conductive wires 210, and the ground pads 208 are also electrically connected to the first nodes 146.
Referring to FIG. 4, a molding process is carried out to encapsulate the chip 200, the bonding pads 206, the ground pads 208, the conductive wires 210, the first node 146 and the nodes 176 by a molding compound 220. A plurality of solder balls 230 are formed on the ground pads 172 and the ball pads 174.
However, in the above-mentioned fabrication process, the conductive material has to be filled into the vias by the stencil printing method. This step of utilizing the stencil printing method is complex, and thus the cost is increased. On the other hand, voids often occur inside the conductive material in the vias during the stencil printing process because of poor gap-fill. Therefore, the reliability of the product is reduced.
Accordingly, it is an object of the present invention to provide a CDBGA package and a fabrication method thereof, which can simplify the fabrication process and reduce the production cost.
It is another object of the present invention to provide a CDBGA package and a fabrication method thereof, which can ensure a good electrical connection of the conductive material in the vias, so that the reliability of the device can be improved.
To achieve the above objects and other advantages in accordance with the present invention, the present invention provides a CDBGA package comprising: a thermal dissipating substrate having a chip region located in the center and a circuit substrate region located at a periphery of the chip region; a plurality of conductive bumps formed on the circuit substrate region; a circuit substrate comprising an insulating layer and a patterned trace layer, wherein a plurality of vias are formed in the insulating layer and correspond to the conductive bumps, and the insulating layer is adhered on the circuit substrate region; a plurality of ground pads, ball pads and nodes are formed on the patterned trace layer, wherein the ground pads correspond to the vias, and a hole is formed at the center of each ground pad corresponds to each via; the circuit substrate further comprises a solder mask layer covering the patterned trace layer and exposing the ground pads, ball pads and the nodes; a chip having an active surface and a corresponding back surface, the back surface of the chip is adhered on the chip region, and a plurality of bonding pads are formed on the active surface, wherein the bonding pads are electrically connected to the nodes; a molding compound encapsulating the chip, the nodes and the connecting parts of the bonding pads and the nodes; and a plurality of solder balls located on the ground pads and the ball pads, wherein the solder balls located at the ground pads fill the vias and are electrically connected to the conductive bumps.
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, the present invention provides a method of fabricating a CDBGA package, and the steps of the method comprise: providing a thermal dissipating substrate having a chip region in its center and a circuit substrate region located at a periphery of the chip region; forming a plurality of conductive bumps on the circuit substrate region; forming a circuit substrate, the circuit substrate comprising an insulating layer and a patterned trace layer, wherein a plurality of vias that are formed on the insulating layer correspond to the conductive bumps; adhering the insulating layer on the circuit substrate region; forming a plurality of ground pads, ball pads and nodes on the patterned trace layer, wherein the ground pads are located on the vias, and each ground pad has a hole located in its center and corresponding to each via; forming a solder mask to cover the patterned trace layer and to expose the ground pads, the balls pads and nodes; providing a chip having an active surface and a corresponding back surface, wherein the back surface of the chip is adhered on the chip region, and a plurality of bonding pads are formed on the active surface; electrically connecting the bonding pads to the nodes; performing a molding process, wherein a molding compound encapsulates the chip, the nodes and the connecting portions between the bonding pads and the nodes; placing a plurality of solder balls on the ground pads and the ball pads, wherein the solder balls locating on the ground pads fill the vias and are electrically connected to the conductive bumps.
According to one embodiment of the present invention, the thermal dissipating substrate further comprises a heat spreader and a ground plate, which is located at the circuit substrate and has a cavity exposing the chip region. The chip is electrically connected to the ground plate, and the chip is adhered on a bottom surface of the cavity that is formed in the thermal dissipating substrate.
The insulating layer is made of polyimide material, and the patterned trace layer is defined by etching a copper foil layer using photolithography. On the other hand, there are three fabrication methods of conductive bumps including wire bonding, electroplating and dispensing. The conductive bumps are made of a material selected from a group consisting of gold and silver. A palladium layer is electroplated on the surface of the circuit substrate region.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.